Impact of Saturated Spontaneous Polarization on the Endurance Fatigue of Si FeFET With Metal/Ferroelectric/Interlayer/Si Gate Structure

We investigate the impact of saturated spontaneous polarization (
${P}_{\text {s}}{)}$
of the ferroelectric on endurance fatigue of Si FeFET with Metal/Ferroelectric/Interlayer/Si (MFIS) gate structure. We tune the
${P}_{\text {s}}$
in the range of 25.9–
$6.4 \mu \text{C}$
/cm
²
by changing the gate structure, such as the insertion of a dielectric layer and annealing temperature. When the
${P}_{\text {s}}$
decreases from 12.1 to
$6.4 \mu \text{C}$
/cm
²
, the memory window of the device decreases while the endurance improves. When the
${P}_{\text {s}}$
decreases from 12.1 to
$8.1 \mu \text{C}$
/cm
²
, the memory window disappears. However, when the
${P}_{\text {s}}$
is lower than
$8.1 \mu \text{C}$
/cm
²
, the memory window reappears. Smaller
${P}_{\text {s}}$
leads to a smaller memory window, which reduces the read noise margin of the memory and is disadvantageous to endurance. Whereas smaller
${P}_{\text {s}}$
leads to weaker charge trapping behavior, which is advantageous to endurance. Our work shows that the endurance characteristic is determined by the competition between the above two processes.