Performance modeling for the ATAMM data flow architecture

The algorithm-to-architecture mapping model (ATAMM) is a new marked graph (a class of Petri net) model from which the rules for data and control flow in a homogeneous, multicomputer, data-flow architecture may be defined. This study is concerned with performance modeling for periodic execution of large-grain, decision-free algorithms in such an ATAMM-defined architecture. Major applications are expected to be real-time implementation of control and signal processing algorithms where performance is required to be highly predictable. The computing environment, problem domain, and algorithm execution pattern are described. Performance measures of computing speed and throughout capacity are defined. Performance bounds are established. Resource (computing element) needs are determined for periodic execution of algorithms.<>