Low-Power CMOS Frequency Comparator

This paper is focused on the design and analysis of a fully on-chip frequency comparator (FC) implemented in 65 nm CMOS technology. The proposed FC employs a digital pre-processing stage followed by a rail-to-rail input and output (RRIO) voltage comparator, with low power consumption in units of $\mu$W. Evaluation accuracy is maintained for input frequencies up to 1 MHz. The FC is designed for the supply voltage of 1.2 V. The FC accepts signals with independent duty cycles and delays, without any correlation between the signals, making it an universal building block of more complex integrated systems. Presented simulation results show robustness of the proposed topology over process, temperature and supply voltage variations (PVT). The presented FC was used in complex ultra-low power System on-Chip (SoC).