Educational Processor with Single-cycle Instructions SVEU16

Courses in principles of digital computers usually begin with elementary logic circuits, proceed through increasingly complex ones, and often end with the design of a central processing unit. Such processors are typically simpler to explain than commercial microprocessors, but also often have very limited capabilities. The educational processor presented in this paper has a good balance between simplicity and capabilities. All its instructions, including multiplication and bit rotation, are executed in one clock cycle. The method of encoding and decoding instructions is quite simplified so that the encoding of instructions can be done even manually without tables, and the decoder unit is a simple forwarding of parts of the instruction word to the control bits of multiplexers. The processor is symmetric around the number 16: it has 16 three-operand instructions, 16 registers, each register is 16 bits wide, as well as the address and data bus. It is simulated at the logic gates level, a Verilog implementation on FPGA, and an emulated computer run by an implementation of a Forth interpreter written partly in its machine language.