Design a PnR Flow Implementation for Different IR Drop Targets

This paper describes the development of a Place-and-Route (PnR) flow implementation for different IR drop targets. IR drop is a significant concern in chip design, as it can lead to undesirable effects such as timing violations and power loss. Therefore, optimizing the IR drop is crucial for efficient chip design. In this project, we develop a PnR flow that can handle different IR drop targets, which will be achieved by modifying the placement and routing stages. The flow will be compared to existing PnR flows and evaluated using various benchmarks. The outcomes will show how well the suggested approach works and how it can handle various IR drop targets. Overall, this project will contribute to improving the efficiency and reliability of chip design by providing a flexible PnR flow that can handle different IR drop targets.