0.13-/spl mu/m 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability

This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-/spl mu/m triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm/sup 2/ and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm/sup 2/ and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment.