A CMOS monolithic /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer for DCS-1800

A monolithic 1.8-GHz /spl Delta//spl Sigma/-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-/spl mu/m CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2/spl times/2 mm/sup 2/. To investigate the influence of the /spl Delta//spl Sigma/ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in /spl Delta//spl Sigma/ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints.