Curing Process on Passivation Layer for Backside-Illuminated CMOS Image Sensor Application

We fabricated Al/Al
₂
O
₃
/SiO
₂
/Si and Al/HfO
₂
/Si structures to optimize the passivation layer of a backside-illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS), with the key properties of the newly developed high-
$k$
passivation layer analyzed via border traps, interface traps, and fixed charges. In the first experiment using Al
₂
O
₃
/SiO
₂
bilayer-based structures, different thicknesses of SiO
₂
were applied from 0 to 15 nm. The improvement in their properties was confirmed by applying forming gas annealing (FGA), a type of post-treatment, to all experimental systems. The first experiment results indicated that both the SiO
₂
layer and FGA were effective for chemical passivation. However, a tradeoff occurred in the degree of improvement of the interface trap density (
$\text{D}_{\mathrm {it}}$
) and fixed-charge density (
$\text{Q}_{\mathrm {f}}$
) according to the SiO
₂
layer thickness. Subsequently, in the second experiment using HfO
₂
single-layer-based structures, FGA improved the border trap to a relatively poor extent compared to the first experiment. Nevertheless, FGA improved the electrical characteristics of the HfO
₂
films without any side effects and results in optimal
$\text{D}_{\mathrm {it}}$
and
$\vert \text{Q}_{\mathrm {f}}/\text{q}\vert $
values of
$2.59 \times 10^{11}$
eV
$^{-1}$
cm
$^{-2}$
and
$1.00 \times 10^{12}$
cm
$^{-2}$
, respectively, demonstrating its potential for the passivation layer in BSI CIS applications.