Impact of Joule heating on scaling of deep sub-micron Cu/low-k interconnects

This paper investigates the impact of Joule heating on the scaling trends of advanced VLSI interconnects. It shows that the interconnect Joule heating can strongly affect the maximum operating temperature of the global wires which, in turn, will constrain the scaling of current density to mitigate electromigration and, thus greatly degrade the expected speed improvement from the use of low-k dielectrics. Through a combination of extensive electrothermal simulation and 2D field solver for capacitance calculation, the thermal characteristics of various Cu/low-k schemes are quantified and their effects on electromigration reliability and interconnect delay are determined. The effect of vias, as efficient heat conduction paths, is included for realistic evaluation. Our analysis suggests that Joule heating will be a bottleneck in scaling interconnects and projections of International Technology Roadmap for Semiconductors (ITRS'01) will not be met.