A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices

The introduction of Software-Defined Networking (SDN) separated the control and data forwarding planes, but the data plane still requires a fully programmable packet scheduler that can adapt to different traffic patterns and offer high expressiveness at line rate. The Dynamic Ranking Push-In-First-Out (DR-PIFO) is a novel programmable hardware queue architecture, introduced for the widely-used Portable Switch Architecture (PSA) used in modern network switches and routers. With the aid of a re-ranking mechanism, the DR-PIFO offers a flexible and expressive solution for a wide range of scheduling algorithms while still meeting line rate requirements. Our design, synthesized using TSMC’s 65nm technology, achieves the desired timing rate of 1GHz while maintaining a throughput that matches the fastest existing schedulers and incurs a mere 15.5% increase in area compared to the state-of-the-art PIFO design. The proposed DR-PIFO’s hardware implementation is shown to closely approach the behavior and performance of its algorithmic model by efficiently executing various scheduling algorithms, leading to precise bandwidth distribution among traffic flows. Additionally, the DR-PIFO offers a significant reduction in the relative flow completion time (FCT) errors, exhibiting a minimum of 30% less error compared to the previously proposed models when implementing various scheduling policies with workloads collected from data centers. Thus, we believe that the DR-PIFO is a significant step toward making hardware packet schedulers more programmable.