A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DLL-Based Three-Segment Hybrid DTC in 28 nm CMOS

This article presents a fully integrated digital polar transmitter (DPTX) incorporating an efficiency-enhanced digital power amplifier (DPA) and a high-resolution digital-to-time converter (DTC). The proposed single-ended Doherty (SED) PA topology with switched-capacitor (SC) arrays can generate four power efficiency peaks that significantly improve the power-added efficiency (PAE) at the power amplifier (PA)’s power back-offs (PBOs). In addition, this work utilizes a three-segment DTC, built with a delay-locked loop (DLL), to improve the phase resolution and enable real-time process-voltage-temperature (PVT) calibration of the DTC. Fabricated in a 28 nm CMOS technology, the DPTX achieves a peak output power (
$P_{\mathrm {out}}$
) of 27.7 dBm and a peak PAE of 33.4% at a 2.1 GHz carrier frequency. The PAEs at 2.5, 6, and 12 dB PBOs are 31.1%, 24.5%, and 18%, respectively. With the 2.1 GHz carrier, the DTC achieves 360° full output phase range, ±1.3° differential nonlinearity (DNL), ±1.7° integral nonlinearity (INL), and −133.86 dBc/Hz phase noise at a frequency offset of 1 MHz, while the power dissipation is only 14 mW. When testing the 10 MHz (and 20 MHz) long term evolution (LTE) 64 QAM signals with a 6.2 (5.0) dB peak-to-average power ratio (PAPR), the DPTX achieves an average
$P_{\mathrm {out}}$
of 21.5 (22.7) dBm, an average PAE of 23.5% (24.6%), an average system efficiency (SE) of 22.5% (23.8%),–30.6 (–27.7) dB error vector magnitude (EVM), and–34.2/–32.6 (–30.1/–29.2) dBc adjacent channel leakage ratio (ACLR). Note that these results have been achieved with only the ON-chip digital pre-distortion (DPD) algorithm.