Rapid interconnect development using an area accelerated electron beam inspection methodology

This paper describes how a new defect inspection technology and methodology was employed to accelerate the process development and integration learning cycles of a 130 nm advanced logic device. The advanced yield management technique to be described is designed specifically for back-end-of-line (BEOL) module development. Through case studies, the application of this technology for process and integration development is demonstrated. Specifically, we discuss how the application of this technology accelerates the development cycle by allowing for a greater number of cycles of learning. The devices used in this study employed a low k dielectric (k < 3.0), a SiC etch-stop scheme, and several levels of Cu interconnect.