Security Region Modeling and Fault Ride-Through Coordinative Control of VSC-HVDC Under Grid Fault

The accumulation of imbalanced power during the fault leads to a rapid rise in DC voltage, which threatens the security of voltage source converter-based high voltage direct current (VSC-HVDC). Existing studies use the dynamic braking resistor, power regulation of sending-end grid, or reactive power control to avoid DC overvoltage or support grid voltage. However, the interaction between active and reactive power control and the relationship between security of receiving-end converter (REC) and duration of imbalanced power are ignored, the dynamic braking resistor or the power regulation of sending-end grid could be triggered unnecessarily, and grid voltage could not be supported effectively. An ideology of dynamic security region (DSR) is proposed. The active and reactive currents of REC are used to characterize DSR, which avoids DC overvoltage and AC overcurrent. The shrinkage of DSR with duration of imbalanced power is found. Further, the concept and calculation method of maximum permissible duration of imbalanced power are proposed. Considering the dynamic property of DSR, the fault ride-through method of VSC-HVDC based on active and reactive current coordination is proposed. Simulations show that the method can strongly support grid voltage while minimizing the activation of dynamic braking resistor or power regulation of sending-end grid.