A 4/5 or 8/9 High-Speed Wide Band Programmable Prescaler

In order to improve the frequency of phase-locked loop (PLL), a high-speed divider-by-4/5 and 8/9 dual modulus prescaler are proposed. The speed of the prescaler is improved on two levels. At the top level, the proposed work reaches high speed with the multiplier, logic gates, and synchronous divider-by-2/3 prescaler. At the gate level, speed optimization is achieved by TSPC DFF embedded with a logic gate. Fabricated in SMIC 0.13-μm CMOS process, the frequency of the proposed circuit ranges from 500M to 8.5G. The power consumption is 1.16 mW at the maximum operating frequency under 1.2 V supply voltage.