An Offline Calculation and Analysis Method of Chips Patch Efficiency for Dual-Arms Mounter to Guide Parameter Optimization

Since high efficiency and low cost have become the leading trend of semiconductor packaging, dual-arms chips mounters have been widely used to eliminate the time delays and improve the efficiency. However, the auxiliary motion is required to avoid spatial interference, which increases the complexity of trajectory. In addition, the motion parameters need to be constantly adjusted online to balance the chips patch efficiency and operation stability, whereas chips placement efficiency needs to online monitor, which is laborious, difficult to adjust the motion parameters rapidly. To offline analyze the packaging efficiency, this article establishes a calculation model for chips patch efficiency of dual-arms mounter, which accurately establish the quantitative relationship between motion parameters and efficiency, narrowing the selection range of motion parameters. First, the process sequence of chips patch is constructed, and the efficiency calculation model is established. Second, considering the characteristics of the time-varying displacement, the method for solving the running time of each process under the flexible velocity control is proposed. Then, the chips patch efficiency is calculated for different parameters, and the effects of the motion parameters and the lead frame structures on chips patch efficiency are investigated, so as to optimize motion parameters, and simulation and calculation results of point to point (PTP) motion are in good agreement with the experimental results, which provide an effective guidance for accurately calculating chips patch efficiency offline and lay a foundation for selecting motion parameters.