A Hybrid PWM Strategy for Switching Loss Reduction in Three-Level Inverters

The advanced bus-clamping pulsewidth modulation (ABCPWM) sequences are well known to reduce line current total harmonic distortion (THD) in a three-level neutral point-clamped (3LNPC) inverter. This article deals with ABCPWM sequences employed optimally to achieve minimum switching loss throughout the linear operating region in a three-level inverter. The work extensively analyzes the performance of these sequences in terms of inverter switching loss and compares them with centered space vector pulsewidth modulation (CSVPWM). Based on the analysis, a hybrid pulsewidth modulation (PWM) scheme termed switching loss reduction (SLR) is proposed by optimally employing ABCPWM sequences in conjunction with variation in power factors (PFs). At a given average switching frequency, the proposed hybrid scheme reduces inverter switching loss compared to CSVPWM and the recently proposed discontinuous PWM (DPWM)-based optimization strategy at all PFs and modulation indices. With this scheme, switching loss reduces to 22%–36% compared to CSVPWM and a maximum of 12% reduction than the existing optimization strategy. Furthermore, the scheme gives lower harmonic distortion compared to these two existing PWM schemes near high modulation indices and near unity PF (UPF) load. The theoretical, simulated, and real-time simulation results are presented with experimental results using the TMS320F28335 DSP controller for validating the proposed work.