Implementation and Research of Vivado HLS’s Function on FPGA

Vivado HLS is a high-level comprehensive tool, which can be well applied to FPGA boards. It can help engineers overcome the difficulties when they are developing in Register Transfer Level (RTL). This paper will use Matlab language and C++ language to design an adaptive notch filter, and verify results of the output by Vivado HLS through the waveform output in Matlab, The "Test bench" and "Co-simulation" in the software are used for collaborative verification to test its real efficiency and functionality. Practice has proved that the best scheme obtained by Vivado HLS can well meet the application requirements after multiple optimizations and iterations. Using its own capabilities, the time of development, debugging and verification is greatly reduced.