A novel asymmetric gate recess process for InP HEMTs

An asymmetric gate recess process has been developed for the fabrication of InP-based HEMTs with improved breakdown voltage. This process is based on a double e-beam exposure of a 4-layers stack of PMGI and PMMA resists. Vertical patterns can be fabricated that can otherwise not be achieved with standard e-beam lithography processes. A 30% improvement of the on-state breakdown voltage of 0.2 /spl mu/m InP HEMTs was obtained without marked degradation of f/sub max/.