An Efficient Design and Performance Analysis of Novel 8 Bit Modified Wallace Multiplier Using Sklansky Adder in Comparison with Kogge-Stone Adder (KSA)

Aim: This study aims to compare the delay performance of an 8-bit modified Wallace multiplier utilising the proposed Sklansky Adder and the Kogg-Stone Adder. Materials and Methods: The ModelSim simulation software was used to simulate the design. This software allowed the researcher to visualize the output waveforms and evaluate the performance of the multiplier. VHDL was used to implement the design of an 8-bit modified Wallace multiplier utilising suggested Sklansky Adder and the Kogge-Stone Adder. During the simulation, input data was collected and used to test the multiplier. Different-sized input data were used to evaluate the multiplier's performance under diverse settings. The performance of the multiplier was evaluated in terms of speed and power consumption. The research involved 20 sample data sets, with 10 from each of two groups. The Sklansky Adder and Kogge-Stone Adder were applied to the modified Wallace multiplier, with an equal number of samples for each adder. The performance evaluation was carried out using the G-power software with alpha and beta values of 0.05 and 0.20, respectively. The results were based on a 95% confidence interval. Result: The propagation delay of the novel modified Wallace multiplier utilising the Sklansky adder is 55 ns, which is significantly less than the propagation delay of the Wallace multiplier utilising the Kogge-Stone adder, which is 85 ns. The significance value that was obtained from the analysis was 0.0436 (P less than 0.05), which indicates that there is a statistically significant difference between the two multipliers in terms of the amount of time it takes for propagation. Conclusion: In conclusion, this study demonstrated the effectiveness of the Sklansky Adder in improving the performance of the modified Wallace multiplier. The results of this research could be helpful to designers who are developing applications for digital signal processing and computer arithmetic that demand high-speed operations that consume a modest amount of power.