Design and Implementation of High-Performance PnR Block-Level Design with Timing Placement

Delay of signal distribution in integrated chips due to an increased number of standard cells and macros. Due to the unprecedented delay in timing the performance of the chips can be delimited. Most of the researchers have performed simulation experiments to minimize the timing by reducing the slack and it has produced compromising results with some tradeoffs. This research study intends to minimize the timing delay through efficient slack management place and route strategies. To achieve such reduced timing, macros were placed proximal to the core boundary. The performance of the proposed work is weighted using performance metrics such as data required time, data arrival time, and violated slacks. Our proposed methodology outperforms by reducing the data required time to 32.6%, data arrival time to 73.4%, and violated slack time to 45% in the cases of before and after placement respectively. This makes our approach to be useful in reducing delay and timing for circuits with 40nm technology.