Lowering of Schottky Barrier Height in a Vertical Pillar MOSFET by Deuterium Annealing

The Schottky barrier height (
$\Phi _{\text {B}}$
) is lowered by high-pressure deuterium annealing (HPDA), in a vertical pillar (VP) metal-oxide-semiconductor field effect transistor (MOSFET). Typical device characteristics were comparatively studied before and after HPDA. A change of contact resistance (
${R}_{\text {C}}$
) at a Schottky junction was also analyzed by using a transmission line method (TLM). Moreover, HPDA effects on the
${R}_{\text {C}}$
were characterized on different crystal orientations of silicon, which has a different number of traps. HPDA is more effective to lower the
$\Phi _{\text {B}}$
at (111) orientation than at (100) orientation because a greater number of interface traps can be passivated for an orientation with a high Miller index. Finally, a deuterium peak was physically profiled across the Schottky junction by use of time-of-flight secondary ion mass spectrometry (ToF-SIMS).