Timing Verification and Optimization Method of Spacecraft Signal Processing Circuit

With the wide application of large-scale complex integrated circuits in spacecraft signal processing circuits, some faults such as timing competition and timing coordination metastable state have been found in the application of new integrated circuits in signal processing circuits, which affect the reliable application of complex integrated circuits in spacecraft. By analyzing the timing faults of integrated circuits found in the application process, combined with the application scenarios of digital integrated circuits in spacecraft signal processing circuits, this paper deeply explores the mechanism and causes, puts forward targeted solutions to timing faults and application circuit optimization methods, and effectively verifies the circuit optimization methods. It can effectively guide the design of complex integrated circuits and its application in spacecraft, and has strong practicability.