Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs *

Monolithic 3D (M3D) integration leverages fine-grained monolithic inter-tier vias (MIVs) to achieve significant improvements in power, performance, and area compared to conventional 2D integrated circuits (ICs). However, immature M3D fabrication flows lead to the degradation of device performance and unreliable interconnects between tiers. To improve yield learning, it is essential to perform fault localization at the tier level, which enables targeted diagnosis and process optimization efforts. This paper presents a graph neural network-based (GNN-based) diagnosis framework that efficiently localizes faults to a device tier and susceptible MIVs. The proposed solution offers rapid feedback to the foundry and improves the quality of diagnosis reports. The transferability of the GNN models makes it possible to perform diagnosis on designs with various design configurations without performance degradation. Results for four M3D benchmarks highlight the effectiveness of the proposed framework.