An Optimum Design and Implementation of a 16-bit ALU on CADENCE Using RISC-V Architecture

The Arithmetic Logic Unit (ALU) is the fundamental component of the Central Processing Unit (CPU) that processes data based on logical and arithmetic operations. The performance of the ALU is measured by the logic delay, power consumption, and chip area based on the architecture used. RISC (Reduced Instruction Set Architecture) has become a standard and remarkable platform for people working in the sphere of chip design and programming. The main intent of this paper is to develop an optimum design of a 16-bit RISC-V-based ALU using the CADENCE tool in the EDA Playground along with XILINX ISE Design Suite 14.7. In the proposed design, the ISA delivers an acting interface between hardware and software which is up to 90% more efficient in terms of processing speed as compared to already existing designs in the literature. Furthermore, it is 33% reduced in size and 80% more efficient in terms of power consumption. This allows optimization of the processor in terms of improved power consumption and speed.