Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors

In this study, we examine the effect of interface trap states on the electrical characteristics of single-gated feedback field-effect transistors (FBFETs) using a commercially available computer-aided design simulation package. Interface trap states exist between the channels and the oxide layers, and these trap states act as acceptor-like trap states in regions of higher energy than the intrinsic Fermi energy (
$E_{\mathrm {i}}$
) and as donor-like trap states in regions of lower energy than
$E_{\mathrm {i}}$
in the energy band. The density distribution peaks at
$E_{\mathrm {i}}$
+ 0.28 eV for the acceptor-like trap states and at
$E_{\mathrm {i}}$
– 0.28 eV for the donor-like trap states. The occupation mechanism of these trap states is analyzed by the density of the interface states and trapped charges, the energy band diagram, and the current-voltage curves. In n-channel (p-channel) FBFETs, the latch-up voltage varies by approximately 0.01 V as the acceptor-like (donor-like) trap states increase, whereas the effect of the donor-like (acceptor-like) trap states is negligible. Moreover, the FBFETs exhibit an operating speed of 4 ns and retention time of 900 s during a memory operation, despite the existence of the interface states.