A Novel GGNMOS Macro-Model for ESD Circuit Simulation

A novel macro-model for ESD circuit simulation with only five fitting parameters is proposed. In this model a new topology and a new multiplication factor equation are proposed as well as the extracting method. This modeling approach greatly reduces time and effort required for circuit design while making use of GGNMOS (Gate-grounded NMOS) as ESD (Electrostatic discharge) protection, which is widely used for integrated circuits to protect IOs and power rails. The DC characteristics of GGNMOS and transient behavior of GGNMOS under HBM (Human body model) stress are simulated using both our macro-model and two-dimensional device simulator, Taurus (Synopsys). Good agreement has been obtained.