Analysis and Implementation of Approximate 4-2 Compressors for Approximate Multipliers

An emerging trend in digital design is approximate computing, which trades off the need for precise computation for increased speed and efficiency. These circuits have been the promising solution for energy-efficient designs in error-tolerant applications. In this paper we analyze the previously proposed 4-2 compressors and compare the results for 8x8 multipliers. The designs are implemented in Vivado, and layouts are made using the magic VLSI tool with osu018 library. The experimental results indicate 33.65% area decrease for the compressor compared to exact compressor and 25.15% decrease in the area delay product of 8x8 multiplier compared to exact multiplier.