Memory Compiler Performance Prediction using Recurrent Neural Network

Semiconductor chips incorporate a large number of smaller memories. As memories contribute an expected 25 to 40 percentage of the overall performance, power and area of a product, memories should be planned cautiously to meet the current era system requirements. Memories are highly uniform and can be described by approximately ten different parameters. Thus, memories are typically generate by memory compilers, to enhance PPA utilization in memory compilers, A crux task in the design procedure of a chip is to choose optimal memory compiler parameters, which fulfill the one part of the system requirements while on the other part optimize PPA, we proposed training fully connected RNN to predict PPA outputs given to a memory compiler parameterization. We have used Open RAM for the generation of dataset the dataset consists of the parameters which can predict the PPA of the desired memory and model is training for the prepared dataset in python as Open RAM is also developed using python so it is easy to collect data from it. Using an exhaustive search based optimizer RNN framework which generates neural network predictions, In our method, a recurrent neural network model with different designs yielded accuracy up to 98 percent.