Performance Analysis of Low Power Multiplexer for Communication System

In this paper, a 4:1 Multiplexer has been designed with low power consumption in 180nm and 100nm CMOS design process. This paper presents simulation and comparison of various key parameters like Power dissipation, Delay, Area, Transistor count and Power delay product (PDP) of 4:1 Multiplexer designed with four different design methodologies viz. conventional CMOS design logic, Pass Transistor design logic (PTL), Transmission Gate (TG) design logic and Gate Diffusion Input (GDI) design logic. As the number of transistors used for the design analysis of 4:1 Multiplexer decreases its performance increases. The main goal is to optimize the device performance using different logic design methodologies. Instead of using circuit level power optimization technique, here basic concept of power optimization is being implemented i.e., reducing the number of MOS-transistors by using low power arithmetic components such as PTL, TG, GDI-cell etc. The simulation tool being used is Tanner EDA. This multiplexer is beneficial in communication system.