Comparative Analysis of EEPL and PPL Techniques in 18nm FinFET Technology

Pass Transistor Logic characterizes several logic families by eliminating redundant MOS transistors from the CMOS digital architecture. This logic can be effectively employed to construct the area and power efficient digital logic circuits. At ultra-scaled technology nodes, the performance of circuits based on CMOS technique gives degraded performance. In this work, one-bit adder circuit by using push-pull pass transistor logic (PPL) and energy economized pass transistor logic (EEPL) approaches are designed. FinFET 18nm technology has been used to perform the comparative analysis of these two approaches. The results show that the Power Delay Product (PDP) and Energy Delay Product (EDP) values of EEPL based on-bit adder are 563.13× 10^-15 and 2836. 51× 10²², respectively. While for PPL based design the PDP and EDP values are 7488.74× 10^-15 and 37638.4× 10²², respectively. EEPL based one-bit adder circuit design has demonstrated enhanced transient response in comparison to PPL based one-bit adder.