Design and Implementation of Hybrid Full Adder Based 16-bit Multiplication Using FPGA

In this paper 16-bit multiplication is implemented using higher order compressors such as 4:3, 5:3, 6:3,7:3, 8:4, 9:4, 10:4, 11:4, 15:4 and a higher order compressor based efficient 16-bit multiplier is proposed. Because of use of compressors, we obtain better area, better space than conventional multiplication. To further implementation of compressor-based multiplication, hybrid full adders are introduced by using Nand gates in our design. After introducing hybrid full adders better area, better space is obtained. In this, 16-bit multiplication using Wallace tree structure is developed. The Wallace tree method is applied to determine outcome of binary number multiplication. This approach transfers the result to the following stage after adding binary bits. Verilog HDL is used to implement every module, and Xilinx Vivado is used to create the synthesized modules.