Design and Verification of an Adder-Subtractor Using UVM Methodology

An adder-subtractor is a unique circuit in digital circuits that can perform addition or subtraction. The circuit decides to conduct addition or subtraction depending on the control signal. The Universal Verification Methodology (UVM) is regarded as the standard procedure for evaluating digital circuit designs. UVM is a collection of SystemVerilog classes and other techniques that makes it simple to build sophisticated, reusable verification environments. When verification processes demand randomization, UVM is the most effective. In this paper, we propose a method UVM which provides more automation than earlier methodologies for verification of adder-subtractor circuits using EDA playground.