High Radix Design for Montgomery Multiplier in FPGA platform

Cryptographic systems, such as RSA, ECC, and SHE, rely heavily on the design of modular multiplication. As these systems involve large integers, the bit-width of the modulus is a critical factor in determining performance. Therefore, creating efficient hardware implementation of the Montgomery Multiplier (MM) algorithm is a significant challenge. Specifically, the performance of a modulus with a variable bit-width N is a key consideration. The Montgomery Multiplication algorithm can improve iterative modular multiplications and squaring required for point multiplication. This algorithm puts back the time-consuming divisions with multiplications and shifts, resulting in faster computations. A fixed-precision Montgomery Modular Multiplier with radix 2
^m
(FPR2tm) performs an iterative computation of intermediate results connected to
$m$
bits of the multiplier. However, this method assumes that the bit-width
$N$
of the modulus is fixed. While the intermediate results must be computed around one multiplier bit at a time, the Radix 2 design introduces a significant cycle delay. This delay can be reduced to 1/m when m > 1. Unfortunately, the resulting design is highly expensive in terms of the circuit's delay and area, which prevents the design of a high-radix Montgomery MM. When the radix is greater than 2, the cycle count decreases, but the multiplication becomes the clock period's bottleneck. To address these issues, a variety of low-latency, high-radix Montgomery Multiplication designs are shown in this paper. According to the experimental results, the design achieves a clock period of 41.75MHz and 140 Slice LUTs with low Area-Latency characteristics.