Design and Analysis of Low Power Energy Efficient Spin-based MCML

A drastic improvement is experienced in the field of chip manufacturing and customization. Apart from the evolution of CMOS, and FPGA, there still exists the need for an enhanced circuit that supports parameters like superior performance and power improvement. In this paper, one such attempt is made where an upgraded MCML circuit is proposed that offers enhanced delay performance and improved power. In the upgraded MCML structure, the input i4 is replaced by I
bias
and I
ideal
due to which the transistor count, circuit complexity, and power are reduced to a certain amount. With the proposed structure a reference, full adder, XOR, and AND gate implementation was carried out with respect to the start of the art and the simulation result reveals that the presented structure outperforms the traditional designs showing the better design and reduced energy consumption.