Exploring the Optimized AI SoC Design Flow

While Artificial Neural Network (ANN) has been well developed in different aspects, it is still a hard topic for IC designer to develop an AI SoC that can fulfill the performance requirements while also maintain the balance of power and die area for AI applications. The large design space variations drive the differences of the SoC architecture for different AI applications. The classic approach is to build some kind of high-level analytical model, write up an implementation spec and proceed the HW design. However, the first time you can really quantitatively measure your power and performance KPIs is when you run the SW image and the HW RTL on an emulator or FPGA prototype. This data comes too late in the process from the architecture perspective. Also, the turnaround time is too long for architecture design exploration and optimization. The continue evolving AI algorithms and new market requirements also make the chip design even harder. In this session, we will review the main phase of AI SoC design where should be considered, and the best practices of the joint AI Chip Design Lab with ITRI. The reference design flow that helps to exploring the optimized AI SoC architecture. MobileNet is used as a benchmark application for architecture exploration. How to minimize the power and energy consumption for targeting an inference latency of 4 milliseconds for processing 5 frames of MobileNet (1250frames/sec); HW/SW co-design and the AI SoC reference design that greatly reduce the risks and development cycle.