FPGA Model of Multi-Active-Bridge-Based Cascaded Solid-State Transformer for Real-Time HIL Tests

This paper presents a method for modeling and real-time (RT) hardware-in-the-loop (HIL) simulation of the multi-active bridge (MAB)-based cascaded solid-state transformer (SST). These types of circuits are challenging for the realm of RT HIL simulation testing due to their high switching frequency, large circuit size, and the high number of switches. The proposed method uses an equivalent circuit and switching function approach to model MAB-based SST. The model is implemented on a field-programmable gate array (FPGA) and achieves time steps ranging from 130 ns to 370 ns, depending on the circuit size and allows switching frequencies ranging up to 150 kHz. To demonstrate the effectiveness and performance of the model, a multi-rate HIL RT test bench is developed. A 3-phase three-stage ac-ac system including 100 kHz 5-winding MABs is considered as a case study. To test both HIL and rapid control prototyping simulation, the plant and controller run on two independent real-time simulators, and fiber optic cables are established to exchange measurements and gating pulses. The developed test bench showed high model fidelity and real-time performance in various circuit conditions.