3.3 kV Low-Inductance Full SiC Power Module

In this paper, a high-performance packaging architecture is proposed to push the boundaries of 3.3 kV high-speed, multichip silicon carbide (SiC) half-bridge power module. The proposed structure effectively addresses the well-known parasitic inductance and current sharing challenges. A compact and symmetrical layout, combined with embedded decoupling capacitors and integrated gate resistors lead to a low-inductance, i.e., 6.9 nH in the power loop, and balanced current-sharing packaging design to fully exploit the benefits of the 3.3 kV SiC devices. Furthermore, fabrication process to realize the proposed packaging architecture is developed and presented. Following the recommended fabrication process, a 3.3 kV/200 A full SiC MOSFET half-bridge module has been assembled in a 104 mm×100 m×m24 mm housing. Both static and dynamic performance validations of assembled modules are performed to demonstrate the effectiveness and benefits offered by the proposed packaging architecture.