A Systematic Parasitic Capacitance Extraction Procedure for Three Level Neutral Point Clamped Inverter Modules

This paper develops a cost-effective and accurate procedure for parasitic capacitance extraction for three-level neutral-point-clamped (3L-NPC) inverter modules. Compared to traditional methods, which require full system measurements or open-module configuration to obtain the module parasitic capacitances, this paper simply estimate the parasitic capacitances from the ringing frequency of the common mode (CM) current in the proposed extended double pulse test (eDPT) setup. The proposed analytical method has been verified and compared with the traditional open-module measurement results. The extracted parasitic capacitances have also been used in the CM electromagnetic interference (EMI) model and show good accuracy in predicting the CM noise spectrum compared to the experimental results from a three-phase inverter-filter test bed.