A Capacitor-Less Digital Low-Dropout Regulator With Self-Clocked Operation

A capacitorless digital low-dropout (D-LDO) voltage regulator with built in adaptive sampling clock is proposed for wireless sensor’s power management applications. The D-LDO regulator adopts a coarse-fine control scheme to accelerate the load transient response. In steady state, the regulator operates at fine-tuning mode with a small switch strength and a low clock frequency. Once the output voltage exceeds the boundaries, a coarse-tuning mode is triggered to quickly find out the desired control bits with a large switch strength and a high clock frequency. The sampling clock is generated with the inherent delay of the internal circuit, thus eliminating the dependence on the external clock. In addition, an active analog-assisted loop is introduced to improve the voltage droop. Fabricated in 180 nm CMOS process, the D-LDO regulator regulates the output voltage range from 0.65 V to 1.15 V. At a VOUT of 0.75 V and VIN of 0.85 V, the proposed D-LDO regulator shows a transient response time of 195 ns with an undershoot of 133 mV at a step load alternating between 5 and 30 mA. It attains a peak current efficiency 99.97% and figure of merit 0.016 ps.