Thermal Impact of Solder Voids under Chip of Power Semiconductors

The durability of power semiconductors must be improved to expand the safe operating area (SOA) in order to support various dynamic operations. As one of the efforts to develop highly reliable products having an expanded SOA, we are working on controlling the increase of thermal impedance caused by solder voids. In this paper, we discuss the thermal effect, based on thermal-simulation results, on the solder voids located under the metal-oxide-semiconductor field-effect transistor (MOSFET) chip. In order to simulate the thermal effect of the solder voids, air blocks of different sizes were inserted into the solder under the MOSFET chip of each package. As a result, we confirmed that the maximum temperature in the MOSFET packages increased due to the influence of solder voids. The effect was relatively large, lasting for 10 us ~ 10 ms, and the effect in the area with an outside upper connector was pronounced. Furthermore, we confirmed that there was an effect of the repeated pulses, assuming actual use. We are considering the discovered impact of solder voids to provide high-quality products.