A Low Power SRAM with Fully Dynamic Leakage Suppression for IoT Nodes

Dynamic leakage suppression (DLS) technique has been investigated to suppress the static leakages of static random-access memory (SRAM) cells, but most of the related works focused on implementing the technique only on part of the circuit, leaving room for further improvements to reduce leakage. In this paper, the feed-forward DLS technique is used to construct a low leakage read buffer (RB). The DLS RB is then integrated with DLS cross-coupled inverters as a full DLS SRAM cell. From SPICE simulations based on a commercial 65nm CMOS technology, the proposed DLS RB and DLS SRAM cell with the DLS RB help reduce the leakage power by 73.96% and 49.84%, respectively, compared to the corresponding 4T RB and DLS SRAM cell with the 4T RB. Additionally, a DLS "pseudo-device" is proposed to optimize parameters of transistors and the trade-off between leakage and performance. Lastly, a DLS SRAM array macro using the proposed DLS SRAM cell achieves a maximum operating frequency of 10.9kHz at the minimum operating voltage of 0.4V and a total leakage current of 2.15nA (leakage power of 645fW) scaled up to 4kb at 0.3V suitable for low power data storage at Internet of Things (IoT) nodes.