Digital Filter Design on High speed Communication with Low Power Criteria

The growing popularity of multi standard wireless communications has created a significant need for DSP. Signal filtering is a common DSP procedure. Digital filter applications are found in data communication, speech processing, audio processing, biomedical signal processing, image processing, instrumentation and control. Implementation of digital filters on Field Programmable Gate Array (FPGA) has gained importance in recent years due to flexible reconfigurable architectures. In this article, the design and implementation of digital filters for communication applications, such as SDR and noise cancellers, are discussed. These filters may also reduce noise. Synthesis parameters like resource utilization and maximum frequency of operation are compared with the existing methods. The implementation results show that the proposed methods offer less resource utilization, particularly in terms of the number of multipliers which are more power consuming parts in the FPGA, which inherently indicate low power implementation of the developed methods.