VLSI Design of Saturation-Based Image Dehazing Algorithm

Hazy weather degrades the vividness of the images captured by real-time systems for applications such as object detection, remote sensing, and surveillance systems. This affects the performance of such real-time systems. The hardware implementation of a real-time haze removal system is imperative to solve these problems. Such a solution is proposed in this article. Here, the saturation-based hardware implementation of an image dehazing system is presented. To estimate atmospheric light more precisely, a 15 × 15 window minimum filter is implemented, which uses the downsampled hazy image to estimate the atmospheric light. Furthermore, we have employed saturation-based transmission map estimation, which makes our approach pixel-based rather than patch-based. Unlike existing patch-based methods, the proposed method requires neither an edge detection unit nor an image filtering unit to suppress halo artifacts around edges. The VLSI architecture of the proposed dehazing system comprises seven pipelined stages. It is implemented on FPGA as well as ASIC (65-nm technology node) platforms. The ASIC implementation of the proposed dehazing system yielded a maximum throughput of 624 Mpixels/s, which is fast enough to process 3840 × 2160 resolution at a rate higher than 70 fps with only 13.2k logic gates count.