1-cycle code decompression circuitry for performance increase of Xtensa-1040-based embedded systems

Code compression is known to be an effective technique to reduce the instruction memory size of an embedded system. However code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. In this paper we describe our design of the world's first running prototype of a 1-cycle code decompression circuitry that decompresses Xtensa 1040 instructions on-the-fly. The circuitry is a standalone unit that does not require any modifications on the Xtensa 1040 processor core. We observed an average code size reduction of about 35% of programs running on the system and an average of 45% of performance increase due to the increased bandwidth and memory hierarchy effects.