Design and Performance Analysis of FPGA based DPU using MAC Unit

A huge literature is available in the area of FPGA implementation of DSP algorithms and their architecture. But still, a variety of problems exist, and each method tackled a subset of these problems. The Commonly identified problems are Latency and accuracy issues viewed in all the architectures which have to be minimized. At the same time implementation in less complex Hardware is needed. The design challenge is to have a better trade-off in terms of speed, power, and area. Requirements are generally contradictory in terms of parameters. If we are generating trigonometry functions employing multiplier, adder, and divider, conventional architectures consume more hardware, and computational time increases. In this paper, DPU architecture design which depicts the type of linear systolic array that behaves like an MISD(Multiple instructions on Single Data) is proposed. In this the simulation process and performance parameters report are validated for DPU unit implementation using Xilinx ISE version 14.7 and the MAC unit is implemented on Nexys 4 DDR Artix 7 FPGA board