Multi Rate LFSR/MISR for Testing Efficiency

The power requirements of a chip during a manufacturing test may significantly exceed those of the final product. This increase in power consumption can be largely attributed to the on-chip generation of extremely random test patterns and the resulting expansion in delay. Expertise in low-power test stimulus production for all types of IC testing, including but not limited to external, internal, and embedded, is needed. Abstract In this work, we present a novel MR-LFSR/MISR for high-throughput BIST architecture that is capable of producing results in parallel across many clock periods. In order to accomplish fast tasks, the proposed work introduces a brand-new architecture. These BIST designs can detect a single stuck-at fault in a combinational circuit. This work was done in Xilinx ISE Design Suite 14.4, which is where the Verilog simulations and Vivado syntheses were executed.