8 Bit SAR Low Power Data Converter Design in 90nm Technology for Low Frequency Signal Acquisition

Data convertors are essential in any digital processing system. It is instrumental in acquiring sensor data in a meaningful way. For minimal power uses, an 8 bit Successive Approximation ADC is proposed in this work. It consumes 4. 55uW of power at a supply voltage of 0. S5V. The structure is realized using 90nm CMOS technology using cadence virtuoso. Low power consumption is attained by using SAR logic using d-flip flop and binary weighted capacitive DAC switching. A clock frequency of 2. 5M Hz and the sampling frequency of 20K Hz are being used for simulation purpose.