Design of Risc-V Processing Unit Using Posit Number System

RISC-V is an Open Instruction Set (ISA) architecture which allows the implementation of the custom instruction set. The RISC-V processor was introduced to reduce the instruction set and increase register resource investment. Unlike other ISA designs, RISC-V is offered under an open-source licence. The chip and device manufacturing industries have provided the CPU with substantial support. RISC-V is therefore primarily made to be flexibly expandable and configurable for use in a variety of applications. In RISC-V, the number system is represented in several formats of real number arithmetic. The representation of real numbers in computer are standard IEEE 754 Floating point. It has many impacts like rounding, excess of Not a Number (NaN), signed Zero. By combining these aspects using posit number format, posit processing unit is developed. The Posit number system is alternative to IEEE 754 Floating point representation. Modification to the standard RISC-V ISA which enables conversion of 8 or 16 bit posits to 16-bit IEEE Floating point number to obtain more dynamic range within the given number of bits. The proposed model is to make the chip smaller and lower the power. Low-precision concepts present an improved solution than approximate computing strategies that attempt to accept lower response quality. When compared to floats of the same size, high-precision positions offer more accurate decimals. Posit avoid the illogical error of assigning a value to the NaN (not-a-number).