A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion

In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated carrier. We also employ a phase-domain digital predistortion (DPD) to combat the intrinsic non-linearity of an LC-type digitally controlled oscillator (DCO), thus avoiding the complications of frequency-dependent calibrations. The prototype, implemented in 40-nm CMOS, modulates the carrier in the range of 2.7–3.9 GHz from a 40-MHz reference. The measured EVM is −47 dB for a 60-Mb/s 64-PSK modulation under the case that the phase-modulated output is frequency-divided by
$K=8$
, i.e., when the DCO exhibits the most significant non-linearity due to the large fractional FM bandwidth. When
$K=8$
or 4, the measured EVM remains below −43 dB across the carrier-frequency tuning range and without re-calibrating the DCO non-linearity.