Effect of Single Spinel Phase Crystallization on Drain-Induced-Barrier-Lowering in Submicron Length IZTO Thin-Film Transistors

This study shows the effect of single spinel phase crystallization on drain-induced barrier lowering (DIBL) of indium-zinc-tin-oxide (IZTO) thin-film transistors (TFTs) with submicron channel length. The 0.9-
$\mu \text{m}$
-long amorphous IZTO (a-IZTO) TFT shows a poor DIBL of 318 mV/V. In contrast, a significant improvement in the DIBL is achieved in the single spinel phase IZTO (s-IZTO) TFT, which could be attributed to the suppression of lateral diffusion of oxygen vacancy (
$\text{V}_{\text {O}}{)}$
and low V
_O
defects through crystallization-induced enforcement of metal-oxygen bonds. Consequently, 0.9-
$\mu \text{m}$
-long s-IZTO TFT reveals a small DIBL of 92 mV/V as well as a high field-effect mobility of 90.1 cm
²
/Vs and a low subthreshold swing of 0.1 V/dec. In addition, reliability against external bias temperature stress is considerably improved through single-phase crystallization, leading to an insignificant threshold voltage shift of +0.4 (−0.4) V under positive (negative) bias stress with electric field of 2 (−2) MV/cm at 60 °C for 10,000 s, respectively, in the 0.9-
$\mu \text{m}$
-long s-IZTO TFT.